Design of Ring Oscillator Using Cs-cmos for Mixed Signal Socs

This paper reports design of a ring oscillator using CS-COMS low noise logic family for mixed signal SOCs. Design has been implemented using 180nm technology with 1.8V supply voltage using CSCMOS logic. CS-CMOS logic efficiently reduce switching noise while maintaining the speed as compare to the other logics like CSL, CBL etc. After completion of the design authors have simulated the design in Spectre simulator and obtained the best simulation results. Authors have determined the parameters like phase noise, delay.